The present invention relates to a manufacturing method of a semiconductor device and to the semiconductor device.
In recent years, a gate-to-gate pitch has become increasingly narrower due to the miniaturization of LSI (Large Scale Integration) devices. Consequently, it is extremely difficult to create a contact hole in a region between gates. As a technique to solve such a problem, there is known a self-aligned contact (SAC) structure. There is also known a technique to silicide a surface of a gate electrode made of polysilicon or surfaces of source/drain regions on a surface of a silicon substrate, in order to achieve low resistance and thereby attain high speeds.
Japanese Patent Application Laid-Open No. 2002-184860 describes a technique in which a protective film formed on a conductive portion is previously etched away, the conductive portion is back-filled with an insulator film, and a contact hole open on a semiconductor substrate and a contact hole open on the conductive portion are simultaneously formed by an etching treatment under the same conditions.
Japanese Patent Application Laid-Open No. 2004-327702 describes a configuration in which metal silicides are formed on a source, a drain and a gate electrode of a logic transistor and on a gate electrode of a memory cell transistor, respectively. The patent document states that consequently, it is possible to speed up operation and form a contact for the gate electrode of the memory cell transistor in a self-aligned manner. Thus, it is possible to simultaneously process the gates of the logic transistor and the memory cell transistor.
FIGS. 15 and 16 are cross-sectional views illustrating part of the structure of the memory region of the semiconductor device described in Japanese Patent Application Laid-Open No. 2004-327702, corresponding to U.S. Pat. No. 6,815,768.
Here, an N-type diffusion region 29 is formed on a surface of a P-type well region 11. In addition, a gate oxide film 24, a gate electrode 25, a silicon dioxide film 26, a cap insulator film 27, a silicon nitride film 28, a silicon nitride film 33, and a silicon dioxide film 34 are formed on and above the P-type well region 11 (FIG. 15A). As the cap insulator film 27, a silicon dioxide film is shown by way of example. In addition, the gate electrode 25 is composed of a polysilicon film.
Also shown in FIG. 15A are a pair of trench capacitors 14, isolation regions 15, trenches 16, embedded plate electrodes 17, dielectric film 18, polycrystalline silicon film 19, silicon oxide film 20, polycrystalline silicon film 21 and diffusion regions 32.
After this, the silicon nitride film 33 exposed on the surface of the P-type well region 11 is removed to expose the cap insulator film 27. The cap insulator film 27 and the silicon dioxide film 26 are removed by etching to expose a surface of the gate electrode 25. At this time, a concave portion is formed on the gate electrode 25 inside the silicon nitride films 28 serving as sidewalls. Subsequently, the surface of the gate electrode 25 is silicided to form a metal silicide film 36 (FIG. 15B). After that, a silicon nitride film 37 is formed over the entire surface of the P-type well region 11 to fill the concave portion inside the silicon nitride films 28 with the silicon nitride film 37 (FIG. 15C). Then, the surface of the silicon nitride film 37 is planarized to expose the silicon dioxide film 34 (FIG. 16A). After that, a silicon dioxide film 38 is formed on the entire surface of the P-type well region 11 and the silicon dioxide film 38, the silicon dioxide film 34, and the silicon nitride film 33 are removed by etching, thereby forming a contact hole 39. Subsequently, a conductive material is buried in the contact hole 39 to form a contact 40 (FIG. 16B). On the other hand, in a logic region, the silicon dioxide film 34 and the silicon nitride film 33 are previously removed prior to the step of siliciding the surface of the gate electrode 25 illustrated in FIG. 15B, to expose a substrate surface, though this is not illustrated. Then, the substrate surface is also silicided in the step of siliciding the surface of the gate electrode 25 illustrated in FIG. 15B.
Furthermore, Japanese Patent Application Laid-Open No. 2001-127270 describes a DRAM-embedded semiconductor device in which a DRAM section and a logic section are formed on the same substrate and the entire surfaces of the source/drain regions and the gate surfaces of transistors in at least the DRAM section and the logic section are silicided.
However, the inventor of this application has newly discovered that such problems as described below arise if an attempt is made to form a self-aligned contact and silicide a location where the contact connects to a silicon substrate.
These problems will be explained by referring to FIGS. 15 and 16. In order to form silicide on a surface of the silicon substrate, the silicon substrate needs to be exposed prior to silicidation. However, in order to expose the surface of the silicon substrate prior to the step of forming silicide on a surface of the gate electrode 25 illustrated in FIG. 15B, the silicon dioxide film 34 and the silicon nitride film 33 need to be removed by etching. For this reason, there has been the problem that a surface of the P-type well region 11 suffers damage or an element-isolating insulator film (STI: Shallow Trench Isolation) formed on the surface of the P-type well region 11 suffers a film reduction, when the silicon dioxide film 34 and the silicon nitride film 33 are etched.